Variations in the manufacturing process of an integrated circuit device, as well as variations in temperature and voltage during operation of the integrated circuit device (collectively referred to as process-voltage-temperature or PVT) typically result in significant variations in the operational speed of logic of the integrated circuit device. As the operational speed changes, the setup and hold times for various logic components change, thereby typically requiring that other devices that interface with the integrated circuit device be designed toward the worst case scenario for setup and hold times. As a result of these timing constraints, system designers typically are forced to implement more costly, complex and faster interfacing devices. Accordingly, an improved technique for controlling the timing of an integrated circuit device to compensate for PVT variations would be advantageous.
The use of the same reference symbols in different drawings indicates similar or identical items.